Power semiconductor module

ABSTRACT

A power semiconductor module is disclosed. One embodiment includes a multilayer substrate having a plurality of metal layers and a plurality of ceramic layers, where the ceramic layers are located between the metal layers.

BACKGROUND

The invention relates to power semiconductor modules.

Conventional power semiconductor modules include one or more powersemiconductor chips which are arranged on a plane ceramic substratewhich includes a metallization on at least one side. At least one ofsuch ceramic substrates is soldered to a metallic base plate of themodule. To improve cooling, the base plate may be pressed against a heatsink.

The metallized ceramic substrates are pressed against the heat sinkwithout a metallic base plate in between. To reduce the heattransmission resistance between the substrate and the heat sink, a layerof heat conductive paste is required. As the thermal conductivity ofsuch a heat conductive paste is limited, the thickness of the layer ofheat conductive paste needs to be very thin. However, apart from thelocations to which downforce is applied to the substrates, thesubstrates tend to bend upwards, i.e. away from the heat sink. Theresult is a non-uniform thickness of the heat conductive paste.

To avoid this, the downforce is sought to be uniformly distributed overthe substrate. For this, mechanical structures are provided to applypressure onto the substrate all over the substrate area. However, due tothe presence of semiconductor chips, bonding wires etc., the options toapply pressure all over the substrate area are limited.

For these and other reasons, there is a need for the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of embodiments and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments andtogether with the description serve to explain principles ofembodiments. Other embodiments and many of the intended advantages ofembodiments will be readily appreciated as they become better understoodby reference to the following detailed description. The elements of thedrawings are not necessarily to scale relative to each other. Likereference numerals designate corresponding similar parts.

FIG. 1 illustrates a vertical cross sectional view of an arrangementwith a power semiconductor module including a single multilayersubstrate as base plate with three metal layers and two ceramic layerswhich is pressed with the multilayer substrate against a heat sink.

FIG. 2 illustrates an enlarged view of an edge area of the powersemiconductor module of FIG. 1.

FIG. 3 illustrates a vertical cross sectional view of a modified edgearea of the power semiconductor module of FIG. 1, wherein a ceramiclayer of the multilayer substrate includes a via which electricallyconnects the metal layers which are arranged on opposite sides of theceramic layer.

FIG. 4 illustrates a vertical cross sectional view of another modifiededge area of the power semiconductor module of FIG. 1, wherein the sidewall of the housing cover of the module is formed to perform a contactpressure against one of the ceramic layers of the module.

FIG. 5 illustrates a vertical cross sectional view of still another edgearea of the power semiconductor module of FIG. 1, wherein the base plateincludes more than three metal layers and more than two ceramic layers,and wherein some of the ceramic layers include vias which are arrangedbelow a semiconductor chip.

FIG. 6 illustrates a vertical cross sectional view of an embodiment of amultilayer substrate where the top layer is a structured metal layer,and which is equipped with power semiconductor chips and power supplyterminals, wherein an output terminal is located opposite the powersupply terminals.

FIG. 7 illustrates a vertical cross sectional view of another embodimentof an equipped multilayer substrate where one of the ceramic layersincludes a number of vias arranged below a power semiconductor chip, andwhere two power supply terminals and an output terminal are arranged inthe same edge area of the multilayer substrate.

FIG. 8 illustrates a vertical cross sectional view of an equippedmultilayer substrate, in which one of the power supply terminals isdirectly soldered or welded to a metal layer which is different from thetop metal layer.

FIG. 9 illustrates a vertical cross sectional view of an equippedmultilayer substrate in which the output terminal is directly solderedor welded to a metal layer different from the top metal layer.

FIG. 10 illustrates a vertical cross sectional view of an equippedmultilayer substrate including four metal layers and three ceramiclayers, where one of the metal layers being different from the top metallayer includes sections which are spaced apart from one another.

FIG. 11 illustrates a vertical cross sectional view of an equippedmultilayer substrate of a power semiconductor module to be pressedagainst a heat sink, where the multilayer substrate is formed convexrelative to the center of the power semiconductor module.

FIG. 12 illustrates a vertical cross sectional view of an equippedmultilayer substrate being pressed against a heat sink and formedconcave relative to the center of the power semiconductor module.

FIG. 13 a illustrates a circuit diagram of power semiconductor moduleincluding a single switch.

FIG. 13 b illustrates a circuit diagram of power semiconductor moduleincluding a single switch, where a number of semiconductor chips areswitched parallel to one another.

FIG. 14 illustrates a circuit diagram of power semiconductor moduleincluding a half bridge (“phase leg”).

FIG. 15 illustrates a circuit diagram of power semiconductor moduleincluding a three phase legs as illustrated in FIG. 14 connectedparallel to one another.

FIG. 16 illustrates a circuit diagram of power semiconductor moduleincluding a three phase legs as illustrated in FIG. 14 with separatephase output terminals (“six pack”).

FIG. 17 illustrates a circuit diagram of power semiconductor moduleincluding a H-Bridge.

FIG. 18 illustrates different processes of a procedure for manufacturinga sub-substrate of a multilayer substrate.

FIG. 19 illustrates different processes of a procedure for manufacturinga multilayer substrate.

FIG. 20 illustrates different processes of another procedure formanufacturing a multilayer substrate.

FIG. 21 illustrates different processes of a procedure for manufacturinga pre-curved multilayer substrate.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific embodiments in which the invention maybe practiced. In this regard, directional terminology, such as “top,”“bottom,” “front,” “back,” “leading,” “trailing,” etc., is used withreference to the orientation of the Figure(s) being described. Becausecomponents of embodiments can be positioned in a number of differentorientations, the directional terminology is used for purposes ofillustration and is in no way limiting. It is to be understood thatother embodiments may be utilized and structural or logical changes maybe made without departing from the scope of the present invention. Thefollowing detailed description, therefore, is not to be taken in alimiting sense, and the scope of the present invention is defined by theappended claims.

It is to be understood that the features of the various exemplaryembodiments described herein may be combined with each other, unlessspecifically noted otherwise.

One or more embodiments provide a power semiconductor module with amultilayer substrate. In one embodiment, the multilayer substrateincludes a group of metal layers with at least a first metal layer, asecond metal layer and a third metal layer, and a group of ceramiclayers with at least a first ceramic layer and a second ceramic layer.The layers of the group of metal layers and the layers of the group ofceramic layers are arranged successively in a vertical direction suchthat the first ceramic layer is arranged between the first metal layerand the second metal layer and that the second ceramic layer is arrangedbetween the second metal layer and the third metal layer. The thirdmetal layer forms the bottom layer of the multilayer substrate. Thesecond ceramic layer includes a top surface facing away from the thirdmetal layer. An electric power circuit of the module includes at leastone power semiconductor chip. A housing cover of the module includes aside wall including a bottom surface facing towards the multilayersubstrate. Between the bottom surface of the side wall and the topsurface of the second ceramic layer an elastic filler is arranged atleast partly.

Another embodiment provides a power semiconductor arrangement includingsuch power semiconductor module and a heat sink. The power semiconductormodule is pressed against the heat sink with the multilayer substrateahead.

Another embodiment provides a multilayer substrate for a powersemiconductor module. The multilayer substrate includes a group of metallayers with at least a first metal layer, a second metal layer and athird metal layer, and a group of ceramic layers with at least a firstceramic layer and a second ceramic layer. The layers of the group ofmetal layers and the layers of the group of ceramic layers are arrangedsuccessively in a vertical direction such that the first ceramic layeris arranged between the first metal layer and the second metal layer andthat the second ceramic layer is arranged between the second metal layerand the third metal layer. The thickness of the first metal layer andthe thickness of the third metal layer is less than or equal to 2 mm.The third metal layer forms an outer surface layer of multilayersubstrate.

FIG. 1 is a vertical cross sectional view of an arrangement with powersemiconductor module 1 which includes a single base plate which isformed as multilayer substrate 3. The power semiconductor module 1configured is to be pressed against a heat sink 9 using screws 5. Afterinserting the screws 5 into mounting holes 6 the screws 5 are screwed ininternal threads 9 a of the heat sink 9 and the power semiconductormodule 1 is detachable connected with the heat sink 9. The downforcegenerated by the screws 5 affects mounting areas 4 a of a housing cover4 of the semiconductor module 1. Thus, the multilayer substrate 3 ispressed against the heat sink 9 by the lower parts of the side walls 4 dof the housing cover 4. Whereas conventional power semiconductor modulesrequire a base plate to which the module is mounted before the module ispressed against a heat sink, in the power semiconductor module 1according to the present invention such an additional base plate isdispensable, i.e. the power semiconductor module 1 may be presseddirectly against a heat sink 9 with the multilayer substrate 3 ahead.Optionally, a heat conductive paste may be arranged between themultilayer substrate 3 and the heat sink 9. Instead of or in addition toscrews 5 any other mechanism may be applied to directly or indirectlypress the multilayer substrate 3 against the heat sink 9.

The multilayer substrate 3 includes three metal layers 11, 12, 13 andtwo ceramic layers 21, 22 which are arranged in succession andalternately in a vertical direction v. Between any two of the metallayers II, 12, 13 at least one of the ceramic layers 21, 22 is arranged.

Metal layer 11 is the top layer of the multilayer substrate 3, i.e. thelayer facing to the inner area of the module 1, and structured intosections 11 a, 11 b, 11 c, 11 d, 11 e, 11 f. The sections 11 a-11 f mayform conductive lines and/or conductive areas. To the sections 11 a, 11c, 11 d, 11 f power semiconductor chips 40 are directly joint and/orelectrically connected by use of a bonding layer 41, e.g., a softsolder, a conductive adhesive, or a silver including layer which is theresult of a low temperature joining technique (LTJT). The powersemiconductor chips may be, for example, a controllable powersemiconductor such as, e.g., MOSFETs, IGBTs, Thyristors, or powerdiodes. The upper sides of the power semiconductor chips 40 areconnected to one another or to sections 11 b, 11 e of the topmetallization 11 by bonding wires 42. The bonding wires 42 may be, e.g.,wires made of aluminum or of an aluminum alloy, e.g., analuminum-magnesium alloy, or wires made of copper or a copper alloy. Thebonding may be done, e.g., by ultrasonic bonding. Instead of bondingwires 42 metal clips may be provided which are joined by a lowtemperature joining technique (LTJT).

Power semiconductor chips are semiconductor chips with high and/or highvoltage ratings. For example, the current ratings may be greater than 50A or greater than 75 A, the voltage ratings more than, e.g., 500 V.Moreover, the power semiconductor chips may include chip sizes of morethan 5.5 mm×5.5 mm, or of more than 7 mm×7 mm.

To externally connect the power semiconductor module 1 to, e.g., a powersupply, a load, a control unit, etc., terminals 31, 32 and 34 areprovided. The terminals 31, 32 may, e.g., be formed as power supplyterminals and be electrically connected and/or mechanically joint to thesections 11 a, 11 b, 11 c, 11 d, 11 e, 11 f. The terminals 34 may be,e.g., control terminals for controllable ones of the power semiconductorchips 40, or output terminals to provide information regarding thestatus of the module 1.

Above the power semiconductor chips 40 an optional printed circuit board(PCB) 8 for interconnecting internal driving terminals is provided. Theprinted circuit board 8 may also be equipped with control electronicsfor controlling the controllable ones of the power semiconductor chips40. Power semiconductor modules including control electronics are alsoreferred to as intelligent power modules (IPM).

The lower part of the power semiconductor module 1 is potted with anoptional soft potting 51, e.g., silicone gel. The soft potting 51 mayextend in the vertical direction v from the multilayer substrate 3 atleast beyond the bonding wires 42, e.g., to the printed circuit board 8.Above the soft potting 51 an optional hart potting 52, e.g., of epoxy,is arranged to electrically insulate and mechanically stabilize theterminals 31, 32 and 34 and the printed circuit board 8. Alternatively,instead of hard potting 52 a soft potting, e.g., silicone, may beprovided. Furthermore, the whole power semiconductor module 1 may befree of any hard potting, e.g., epoxy.

Terminals mounted directly on the multilayer substrate 3 the module mayinclude terminals which are incorporated in a plastic frame, e.g., inthe housing cover or in a housing cover, and be bonded by wires orribbons etc. to the multilayer substrate 3 or a device, e.g., asemiconductor chip 40 mounted thereon, and/or to the printed circuitboard 8 or a device, e.g., a control circuit, mounted thereon.

Along the outer edges of the multilayer substrate 3, an optional filler7 is provided for cushioning the down force effecting the multilayersubstrate 3. Instead of a filler 7 different from soft potting 51 thefiller 7 may be a part of the soft potting 51. Such cushioning isimportant as modern power semiconductor modules 1 may include a largenumber of power semiconductor chips 40 which requires a multilayersubstrate 3 including a large area, e.g., of greater than 6 cm×8 cm. Forexample, the power semiconductor chips 40 may be arranged in more than 2rows and more than 2 columns, i.e. the number of power semiconductorchips 40 mounted to the multilayer substrate 3 may be more than or equalto 9, or, e.g., more than or equal to 24, or more than or equal to 36.

In one embodiment, filler 7 may be used to electrically insulate atleast some of the metal layers 11, 12, 13 from one another. Aside fromthat, the filler 7 distributes the down pressure from the side wall 4 dof the housing cover 4 affecting the multilayer substrate 3 when thesemiconductor module 1 is pressed against the heat sink 9 with themultilayer substrate 3 ahead. The filler 7 may include a hardness shoreA of less than 85, or less than 65. To ensure a required rigidity,hardness shore A of filler 7 may be greater than, e.g., 20, or greaterthan 40.

If the housing cover 4 of the power semiconductor module 1 is pressedagainst a heat sink with the multilayer substrate 3 ahead, filler 7 willbe compressed, i.e. filler 7 causes a cushioning effect. The effectivelength d7 of filler 7 being relevant for that cushioning effect is thesmallest dimension of the filler 7 that appears between a bottom face 4f of the side wall 4 d and the multilayer substrate 7 in the verticaldirection. When the filler 7 is not compressed, i.e. when the powersemiconductor module is not pressed against a heat sink, the effectivelength d7 may be from 0.1 mm to 1 mm, or from 0.3 mm to 2 mm. It ispointed out that the surface 4 f is designated as bottom surface becauseit is facing away from the upper side 4 h of the housing cover andtowards the multilayer substrate 3. A “bottom surface” of the side wall4 d is not necessarily that 4 g of some surfaces 4 f, 4 g of the sidewall 4 d facing away from the upper side of the housing cover, which isfurthermost distant from the upper side.

As the multilayer substrate 7 protrudes the mounting area 4 a in thevertical direction towards the exterior of the power semiconductormodule 1 by a distance d1, filler 7 will be compressed if the powersemiconductor module 1 is pressed by use of the mounting area 4 aagainst a heat sink with the multilayer substrate 3 ahead. The distanced1 may be, e.g., from 0.1 mm to 1 mm, or from 0.1 mm to 0.5 mm, or from0.3 mm to 2.0 mm.

The power semiconductor module 1 includes an electrical circuit with theat least one power semiconductor chip 40. This electrical circuit iselectrically connected to at least one of the metal layers 11, 12, 13 ofthe multilayer substrate 3.

Hence, the border area, of the metal layers being electrically connectedto the electrical circuit may be completely electrically insulated. Inthis spirit, the border area of a metal layer is the area which isaccessible between the ceramic layers 21 22 adjacent to the respectivemetal layer.

In general, all metal layers of the multilayer substrate 3 which areelectrically connected to the electrical circuit may be completelyinsulated against any contact with air or gas inside and surrounding themodule 1. The insulation may be realized by use of the soft potting 51and/or the filler/glue 7. In FIG. 1, the bottom metal layer 13 isfloating, i.e. not connected to the electrical circuit and therefore notcompletely insulated against contact with air or gas.

Optionally, the bottom layer of all metal layers 11, 12, 13 of themultilayer substrate which are electrically connected to the electricalcircuit and all above metal layers may be insulated, e.g., at least intheir boarder areas or completely, against contact with air or gas.

For assembling the power semiconductor module 1 the prepared multilayersubstrate 3 may be equipped with the power semiconductor chips 40, thebonding wires 42, the printed circuit board 8, the bus bars 35 and 36,and the terminals 31, 32 and 34. Then, the equipped multilayer substrate3 may be inserted with the terminals 31, 32, and 34 ahead in the housingcover 4 and glued to the side wall 4 d of the housing cover 4. The gluemay be applied additionally to the filler 7. Alternatively, the filleract both as filler and glue. Materials suitable as filler and/or glueare, e.g., silicone rubber or any other elastic glue.

FIG. 2 illustrates a magnified section of the power semiconductor module1 of FIG. 1. The section includes a mounting area 4 a, the lower part ofthe side wall 4 d and an outer edge of the multilayer substrate 3. Thelower part of the side wall 4 d includes a recess in which themultilayer substrate 3 and the top metal layer 11 extend in the lateraldirection r. The gap between the side wall 4 d and the multilayersubstrate 3 is filled with filler 7. Each of the layers 11, 21, 12, 22,13 of multilayer substrate 3 includes a main face facing towards theupper side of the housing cover 4, and a further main face facing awayfrom the upper side of the housing cover 4. Each of the main faces ofthe layers 11, 12, 13, 21, 22 of the multilayer substrate 3 includes anouter edge 11 k, 12 k, 13 k, 21 k and 22 k, respectively. In the contextof the present invention the expression “outer edge” of a layerindicates an outer edge of the complete respective layer, which means,e.g., that an edge of a layer including sections distant from oneanother is not referred to as “outer edge” if it faces towards anothersection of that layer.

Filler 7 insulates the outer edges 11 k, 12 k of metal layers 11 and 12,respectively, the outer edges 21 k of ceramic layer 21, and the outeredge 22 k of ceramic layer 22 facing towards the center of the module 1.Such an insulation may be required if a high voltage, e.g., more than1500 V, shall be applied to metal layers 11 and/or 12, as a contactbetween air and the metal layer may result in a partial discharge of themetal layer. In the embodiment of FIGS. 1 and 2, the bottom metal layer13 of substrate 3 is electrically insulated against the metal layer 12next to it and against the electric power circuit of the module by thebottom ceramic layer 22. Therefore, filler 7 covers only the outer edgesof the upper metal layers 11 and 12 but not of the bottom metal layer13.

The multilayer substrate 3 includes three metallization layers 11, 12,13 and two ceramic layers 21, 22, which are arranged in the verticaldirection v. Optionally, the multilayer substrate 3 may includeadditional metal layers and/or additional ceramic layers. One, some orall of the metal layers 11, 12, 13 may include thicknesses d11, d12, andd13, respectively, ranging from 0.05 mm to 2 mm, or from 0.25 mm to 2.5mm. The ceramic layers 21, 22 may include thicknesses d21 and d22,respectively, ranging from e.g., 0.1 mm to 2 mm, or from 0.25 mm to 1mm. The bottom metal layer 13 of the multilayer substrate 3 may includea thickness d13 of, e.g., less than 2 mm or less than 1 mm.

In the embodiment of FIG. 2, the metal layers 11, 12, 13 includeidentical thicknesses d11, d12 and d13, respectively, e.g., 0.5 mm. Theupper ceramic layer 21 includes a thickness d21 of 0.25 mm, the lowerceramic layer 22 a thickness d22 of 0.38 mm or of 0.63 mm. The thicknessd22 of the bottom ceramic layer 22 of the ceramic layers 21, 22 of themultilayer substrate 3 may be greater than or equal to the thickness d21of any other ceramic layer 21 of the multilayer substrate 3. Further,the thickness d13 of the bottom ceramic layer 22 of the multilayersubstrate 3 may be, e.g., less than 2 mm or less than 1 mm. In thelateral direction r, the ceramic layers 21, 22 extend beyond the metallayers 11/12 and 12/13, respectively, which are arranged next to therespective ceramic layer 21, 22. In particular, if the bottom layer 13of the multilayer substrate 3 is a metal layer, the bottom ceramic layer22 may extend beyond that bottom metal layer 13 in each lateraldirection r being perpendicular to the vertical direction v.

The down pressure with which the multilayer substrate 3 is pressedagainst the heat sink 9 may be generated by use of a fastener in amounting area 4 a which may be a part of the housing cover 4. In theembodiment of FIGS. 1 and 2, the mounting area 4 a includes mountingholes 6. The mounting area 4 a which is provided at the exterior of thehousing cover 4, may include plastic and/or metal parts and may beelastically attached to the housing cover 4 by use of an elasticconnection 4 b. The elastic connection 4 b serves as pressure transferelement and as shock absorber. Such elastic connection 4 b is designedwith respect to the required down pressure and elongation and may beformed as elastic element, e.g., made of or including metal and/orplastics, for example an elastic metal or a plastic bend or a plasticsheet. An elastic connection 4 b may be an integral part of the housingcover 4, e.g., a bar of a housing cover made of plastics. Alternatively,an elastic connection 4 b may be joined to the housing cover 4, e.g.,moulded to it.

A modification of FIG. 2 illustrates FIG. 3 where at least one ceramiclayer 22 of the ceramic layers 21, 22 of the multilayer substrate 3includes one or more vias 10. The vias 10 may serve to electricallyconnect the metal layers 12 and 13 adjoining to opposite sides of theceramic layer 22 in which the via 10 is formed. For example, the vias 10may be formed cylindrical or as cylinder ring and include a diameter Dof, e.g., less than 5 mm, or from 1 mm to 2.5 mm. In FIG. 3, the bottomlayer 13 of substrate 3, i.e. the layer facing away from the center ofthe module 1, is a metal layer which is electrically insulated againstthe electric power circuit of module 1. However, an electric fieldgenerated by the electric power circuit may couple into bottom metallayer 13 and cause an electrical discharge in particular in the area ofthe outer edges 13 k of bottom metal layer 13, as the highest strengthof electric field occurs at locations where the surface of the metallayer includes its smallest radius of curvature. To reduce or avoid suchelectrical discharge, bottom metal layer 13 and the metal layer 12 nextto it are electrically connected by at least one via 10, butelectrically insulated against the electrical power circuit of themodule 1 and, optionally, against all other metal layers 11 of thesubstrate 3. As metal layer 12 is electrically connected to the electricpotential of bottom metal layer 13, the strength of the electric fieldthat occurs at the outer edges 13 k is reduced compared with theelectric field that occurs at the outer edges 13 k when the bottom layer13 is electrically insulated against metal layer 12 next to it, becausetwo metal layer with four outer edges 13 k, 12 k instead of only onemetal layer with two outer edges 13 k are connected to the same electricpotential.

The ceramic layer 22 is arranged between the bottom metal layer 13 andthe metal layer 12 next to the bottom metal layer 13. The upper of theouter edges 22 k of the ceramic layer 22 faces away from the bottommetal layer 13. Filler 7 covers, e.g., completely, at least that upperof the outer edges 22 k. Optionally, filler 7 may also cover the outeredges 12 k, 21 k and 11 k of one, some or all layers 12, 21, 11 ofsubstrate 3 which are arranged on the side of ceramic layer 22 facingaway from the bottom metal layer 13.

As also illustrated in FIG. 3, an optional mechanical support may beapplied to the multilayer substrate 3 by one or more posts 4 c which arespaced apart from the outer edges of the multilayer substrate 3. Theposts 4 c may be a part of the housing cover 4 or be separate therefrom.

In the embodiments of FIGS. 1, 2 and 3, the down pressure from the sidewall 4 d of the housing cover 4 affects the top layer 11 of themultilayer substrate 3. Alternatively, as illustrated in FIG. 4, it isnot required that the down pressure affects the top metal layer 11 ofthe multilayer substrate 3. In the embodiment of FIG. 4, the downpressure caused by the side wall 4 d of the housing cover 4 affects theceramic layer 22. To allow for this, the ceramic layer 22 extends beyondthe above layers 11, 21 and 12 of the multilayer substrate 3.

As can be seen from FIG. 5, the multilayer substrate 3 may also includemore than three metal layers 11, 12, 13, 14 and more than three ceramiclayers 21, 22, 23. To improve heat dissipation from a powersemiconductor chip 14 being disposed on the multilayer substrate 3, one,some or all of the ceramic layers 21, 22, 23 of the multilayer substrate3 may include a number of vias 10 in their respective areas below thepower semiconductor chip 40. Additionally, the vias 10 may serve toelectrically connect adjacent metal layers. In the recess of the lowerpart of the side wall 4 d of the housing cover 4 an optional trench 4 eis provided. This trench 4 e serves as reservoir for filler 7 whengluing the multilayer substrate 3 to the housing cover 4.

From FIGS. 2 to 5 it can be seen that if the power semiconductor module1 is attached to but not yet pressed against a heat sink with themultilayer substrate 3 ahead, the housing cover 4 is distant from theheat sink. When down pressure increases, filler 7 will be compressed.However, the down pressure affecting the multilayer substrate 3 may belimited to a predefined value by dimensioning the distance d7 and/or thedistance d3 between the lower end of the side wall 4 d and the bottom ofthe multilayer substrate 3 in the vertical direction v. This limitationresults from the lower end of the side wall 4 d which will contact theheat sink when the down pressure increases. As soon as the side wall 4is in contact with the heat sink, a further increasing down forceaffecting the housing cover 4 will not result in a further increasingdown force affecting the multilayer substrate 3. The distance d3 mayrange, e.g., from 0 μm to 50 μm, or from 50 μm to 300 μm.

A further limitation of the down force affecting the multilayersubstrate 3 may be achieved by determining the distance d2 between theside wall 4 d of the housing cover 4 and the center of the mountingholes 6. The distance d2 may be, e.g., greater than or equal to 10 mm.

FIG. 6 is a vertical cross sectional view of a multilayer substrate 3equipped with power semiconductor chips 40 and with terminals 31, 32 and33. The power semiconductor chips 40 are electrically connected to forma half bridge. The electrical connections of the equipped multilayersubstrate 3 are realized by bonding wires 42 and by sections 11 a, 11 b,11 c, 11 d of the top metal layer 11, vias 10 and the metal layer 12.The terminals 31, 32 may be soldered or welded to the sections 11 d, 11c, respectively, and serve as power supply terminals. Accordingly, theterminal 33 may be soldered or welded to the section 11 a of the topmetal layer 11 and serve as phase output layer. The electricalconnection between the bottom of one of the power semiconductor chips 40(the left one in FIG. 3) and the power supply terminal 31 is realized byuse of the bonding layer 41, vias 10 and metal layer 12. For example,the power supply terminals 31, 32 on the one hand and the phase outputterminal 33 on the other hand may be arranged in opposite boarder areasof the multilayer substrate 3.

As can be seen from FIG. 7, the power supply terminals 31, 32 and thephase output terminal 33 may be arranged within the same boarder area ofthe multilayer substrate 3.

According to another embodiment which is illustrated in FIG. 8, thepower supply terminals 31, 32 are arranged in the same boarder area ofthe multilayer substrate 3, whereas the phase output terminal 33 isarranged in the inner area of the multilayer substrate 3. Likewise, thephase output terminal 33 may be arranged in a boarder area of themultilayer substrate 3, whereas the power supply terminals 31, 32 arearranged in an inner area of the multilayer substrate 3, which can beseen from FIG. 9. In FIG. 8 the power supply terminal 31 and in FIG. 9the phase output terminal 33 are not soldered or welded to the top metallayer 11 but to another 12 of the remaining metal layers 12, 13. In FIG.9, metal layer 12 includes sections 12 a and 12 b which are arrangeddistant and electrically insulated from one another by a dielectric 15.

In the embodiments of FIGS. 6 to 9, the bottom metal layer 13 of themultilayer substrate 3 is electrically insulated against metal layer 12next to it. Alternatively, the bottom layer of the multilayer substrate3 may also be electrically connected with the power semiconductor chips40.

In the embodiment of FIG. 10, which illustrates an equipped multilayersubstrate 3 with four metal layers 11, 12, 13, 14 and three ceramiclayers 21, 22, 23, the bottom metal layer 14 is electrically connectedto the power supply terminal 31 for the negative power supply voltage.Alternatively, the bottom metal layer 14 may be electrically connectedwith the power supply terminal 32 for the positive power supply voltage,or with the phase output terminal 33. As also illustrated in FIG. 10,for electrically connecting the power semiconductor chips 40 also one ormore of the lower metal layers 12, 13, 14 may be used. In FIG. 10, metallayer 13 includes sections 13 a, 13 b and 13 c which are arrangeddistant from one another and electrically insulated by a dielectric 15.The dielectric 15, e.g., the unsintered “green” ceramics, may be filled,e.g., pressed, in grooves during the manufacturing process of themultilayer substrate, followed by a sintering step. The grooves may befilled with material identical with the material of one of the ceramiclayers 22 or 23 adjacent to metal layer 13 in which the dielectric isarranged. Alternatively or additionally, the grooves may be filled withdielectric potting, e.g., made of plastics, for example polyimide,epoxy, or silicone, via openings which are provided in the metal layersand in the ceramic layers above the groove to be filled. Afterwards, thepotting may be hardened, e.g., during a tempering step.

The embodiments of FIGS. 6 to 10 illustrate multilayer substrates 3being equipped with power semiconductor chips 40 and with terminals 31,32, 33 only. However, these equipped multilayer substrates 3 may becompleted to power semiconductor modules including the options asdescribed with reference to FIGS. 1 to 5 and to below FIGS. 11 to 17.

If a plane multilayer substrate 3 is pressed against the heat sink by adown pressure as explained with reference to FIG. 1 and the downpressure affects the multilayer substrate 3 for instance in its boarderarea, the multilayer substrate 3 will lift off from the heat sink in theinner area of the multilayer substrate 3. Likewise, if the down forcewhich presses the multilayer substrate 3 against a heat sink in theinner area of a plane multilayer substrate 3, the multilayer substrate 3will lift off from the heat sink 9 in the boarder area of the multilayersubstrate 3. In both cases, the heat transmission resistance between themultilayer substrate 3 and the heat sink 9 will increase because of thereduced heat conductivity in the lift-off areas.

As illustrated in FIGS. 11 and 12, this may be avoided by using apre-curved multilayer substrate 3. In FIG. 11, the multilayer substrate3 is pre-curved convex relative to the center of the power semiconductormodule 1 which can be seen from areas 2 in which the multilayersubstrate 3 is spaced apart from the heat sink 9. If a down forceaffects the multilayer substrate 3 in the boarder area of the multilayersubstrate 3 to press the substrate 3 against the plane surface of theheat sink 9, the multilayer substrate 3 will deform from its pre-curvedshape to an almost plane multilayer substrate 3.

In FIG. 12, the multilayer substrate 3 is pre-curved concave relative tothe center of the power semiconductor module 1 which can be seen from anarea 2 in which the multilayer substrate 3 is spaced apart from the heatsink 9. If a down pressure which is created by a center screw 5 andtransmitted by a post 4 c of the housing cover 4 affects the multilayersubstrate 3 in the center area of the multilayer substrate 3, thesubstrate 3 is pressed against the plane surface of the heat sink 9 andthe multilayer substrate 3 will deform from its pre-curved shape to analmost plane multilayer substrate 3. At the lower end of the post 4 c afiller 7 may be provided. This filler may include the same properties asthe filler 7 between the lower ends of the side walls 4 d.

In the embodiments described above the power semiconductor modules mayinclude at least one power semiconductor chip. The following FIGS. 13 to17 illustrate circuit diagrams of embodiments of power semiconductormodules 1 including a multilayer substrate as described above.

FIG. 13 a is a circuit diagram of a single switch power semiconductormodule 1. The single switch includes an IGBT 40 a and an optional freewheeling diode 40 b switched antiparallel to IGBT 40 a. For its externalconnections the module 1 includes terminals 31, 32 for power supply, anda control terminal 34. The IGBT 40 a may consist of a singlesemiconductor chip, or alternatively, as illustrated in FIG. 13 b,include a number of semiconductor chips 40 a switched parallel to oneanother.

FIG. 14 is a circuit diagram of a half bridge power semiconductor module1. The half bridge (“phase leg”) includes an upper leg I and a lower legII. The upper leg I includes an IGBT 40 a and an antiparallel freewheeling diode 40 b, the lower leg an IGBT 40 c and an antiparallel freewheeling diode 40 d. The IGBTs 40 a, 40 c are connected in series.During normal operation, none or one of but not both IGBTs 40 a, 40 care switched on at the same time. Such a half bridge allows forconnecting one of the electric potentials applied to the power supplyterminals 31 and 32 with the phase output terminal 33 and to a load 60connected therewith.

To improve ampacity, instead of just one IGBT and one freewheeling diodeper leg I, II each of the legs I, II may include more than one IGBTand/or more than one freewheeling diode. FIG. 15 is a circuit diagram ofsuch a power semiconductor module 1. The upper leg I includes a numberof IGBTs 40 a′ connected parallel to one another, and a number offreewheeling diodes 40 b′ connected parallel to one another. The IGBTsare connected antiparallel to the freewheeling diodes. In the same way,the lower leg II includes a number of IGBTs 40 c and freewheeling diodes40 d that are connected to one another.

FIG. 16 is a circuit diagram of a power semiconductor module 1 includingthree phase legs L1, L2, L3 as illustrated in FIG. 14. The phase outputsof the phase legs L1, L2, L3 are connected to independent phase outputterminals 33′, 33″, 33′″, respectively, independent from one another.The control inputs of the IGBTs 40 a, 40 c are also independent from oneanother and connected to independent control input terminals 34. Asillustrated in FIG. 16, the phase legs L1, L2, L3 may include commonpower supply terminals 31, 32. Alternatively, one, some or all of thephase legs L1, L2, L3 may include individual power supply terminals.

FIG. 17 illustrates an embodiment of a power semiconductor module 1including a H-Bridge. The module includes two half bridges 1 a and 1 beach of which is designed similar to the half bridge described withreference to FIG. 14. The output of the half bridge 1 a is electricallyconnected to a first phase output terminal 33 a, the output of the halfbridge 1 b to a second phase output terminal 33 b. An external load 61,e.g., a motor, is connected to the phase output terminals 33 a, 33 b.Dependent on input signals applied to control terminals 34 of the module1 the direction of rotation as well as the rotational speed of the motor61 can be varied. For example, if the IGBTs in the upper leg la of halfbridge 1 a and in the lower leg IIb of half bridge 1 b are switched onand the IGBTs in the upper leg Ib of half bridge 1 b and in the lowerleg Ia of half bridge 1 a are switched off, the direction of rotation ofthe motor is opposite to the direction of rotation when the IGBTs in theupper leg Ia of half bridge 1 a and in the lower leg IIb of half bridge1 b are switched off and the IGBTs in the upper leg Ib of half bridge 1b and in the lower leg IIa of half bridge 1 a are switched on.

With reference to FIGS. 13 to 17, a single switch, a half bridge, “sixpack” and a H-bridge have been described. However, other embodiments mayrelate to power semiconductor modules including other configurationsincluding one or more power semiconductor chips, e.g., powersemiconductor modules which are designed as full inverter (“six pack”),or subunits thereof.

The power semiconductor modules described in FIGS. 1 to 12 includemultilayer substrates 3. Each of the multilayer substrates 3 includes atleast three metal layers and at least two ceramic layers. Such a metallayer may, e.g., consist of copper, aluminum, or silver, or include atleast one of these metals, e.g., an alloy. In case of an alloy, alsoother materials may be comprised. Optionally, a metal layer may includesublayers. Each of the ceramic layers of such a multilayer substrate 3may, e.g., consist of or include Al₂O₃ (aluminum oxide), AlN (aluminumnitride), or Si₃N₄ (silicon nitride). The multilayer substrates 3 may bemanufactured using an AMB process (AMB=active metal brazing), a DABprocess (DAB=direct aluminum bonding), or a DCB process (DCB=directcopper bonding).

One way for producing a multilayer substrate is to stack metal layersand ceramic layers alternately and successively and afterwards bondingthe stacked layers to one another by applying pressure and hightemperature to the stack. The required temperature depends on theselected bonding process. The metal layers and/or the ceramic layers maybe structured prior to stacking. Optionally, the ceramic layers may beprovided prior to bonding with openings in which electrically conductivematerial, e.g., copper balls or a silver paste, is inserted. In case ofstacking and bonding structured metal layers and/or ceramic layers themetal layers and/or ceramic layers may be aligned prior to the bondingstep.

In a further way, some of the metal layers and some of the ceramiclayers may be bonded separately to form a sub-substrate. Afterwards,such a sub-substrate may be joined with further metal layers and/orfurther ceramic layers and/or further sub-substrates. As far as it isaccessible, the area of a metal layer of a sub-substrate may bestructured prior to joining the sub-substrate with the further metallayers and/or further ceramic layers and/or further sub-substrates. Asub-substrate may comprise, e.g., one ceramic layer which is joined withone metal layer, or with two metal layers which are arranged on oppositesides of the ceramic layer and joined therewith. For both ways, AMB,DAB, DCB may apply as joining technique. Other techniques are vacuumsoldering, LTJT, TLP soldering (TLP=transient liquid phase), or gluingwith a conductive glue.

FIG. 18 illustrates different processes of a procedure for manufacturinga sub-substrate of a multilayer substrate. According to FIG. 18 a twometal layers 11′, 12′ and a ceramic layer 21′ are provided. In anoptional step, an opening 18 may be created in the ceramic layer 21(FIG. 18 b). In the opening 18 a conductive material 10, e.g., a silverpaste or a copper ball, may be inserted (FIG. 18 c). Afterwards, themetal layers 11′, 12′ and the ceramic layer 21′ may be stacked such thatceramic layer 21′ is arranged between the metal layers 11′, 12′ (FIGS.18 d and 18 e). Between adjacent layers 11′, 12′, 21′ additionalmaterial, e.g., silver paste or glue, may be arranged to improve thejoining properties. Then this stacked arrangement is clamped betweenclamping jaws 20 (FIG. 18 f) such that the layers 11′, 12′, 21′ arepressed to one another. During clamping the temperature of the stack maybe increased. FIG. 18 g illustrates the sub-substrate 3′ after releasingthe pressure. The sub-substrate 12′ including two metal layers 11′, 12′and a via 10 results (FIG. 18 g).

Optionally, grooves 19′ may be produced in at least one of the metallayers 11′, 12′. Due to the grooves 19′ the respective metal layer 12′is divided into sections 12 a′, 12 b′, 12 c′ distant and electricallyinsulated from one another (FIG. 18 h). The grooves 19′ may be producedby conventional masking and etching technique. Alternatively, grooves19′ may be produced by milling.

Instead of producing a sub-substrate including one ceramic layer 12′ andtwo metal layers 11′, 12′, sub-substrates including one ceramic layerand just one metal layer may be manufactured in a corresponding way. Afurther modification may be a sub-substrate including a metal layerwhich is arranged between two ceramic layers.

With reference to FIG. 19 a two sub-substrates 3′, 3″ are provided. Eachof the sub-substrates 3′, 3″ may be produced as described above. Each ofthe bottom metal layer 12′ of sub-substrate 3′ and the top metal layer12″ of sub-substrate 3″ includes a number of grooves 19′. Thesub-substrates 3′, 3″ are stacked and aligned such that the grooves 19′of metal layer 12′ and the grooves of metal layer 12″ match. Betweenadjacent sub-substrates 3′, 3″ additional material, e.g., silver pasteor conductive glue, may be arranged to improve the joining properties.Then this stacked arrangement is clamped between clamping jaws 20 (FIG.19 b) such that the sub-substrates 3′, 3″ are pressed to one another.During clamping the temperature of the stack may be increased. FIG. 19 cillustrates the multilayer substrate 3 after releasing the pressure.Adjacent grooves 19′ of adjacent metal layers 12′, 12″ form grooves 19due to which metal layer 12 which is formed from metal layers 12′, 12″is divided into sections 12 a, 12 b, 12 c distant and electricallyinsulated from one another. Optionally, another grooves 19 may beproduced in at least one of the top metal layer 11 and the bottom metallayer 13 (FIG. 19 d).

Another embodiment for a method of producing a multilayer substrate 3 isexplained with reference to FIG. 20. FIG. 20 a illustrates metal layers11′, 12′, 13′ and ceramic layers 21′, 22′. Ceramic layer 21′ is providedwith an opening 18 which may be filled with conductive material, e.g.,silver paste or copper balls. Metal layer 12′ includes sections 12′a,12′b, 12′c which are distant from one another. After adjusting andstacking the metal layers 11′, 12′, 13′ and the ceramic layers 21′, 22′the stack is clamped between clamping jaws 20 (FIG. 20 b) such that thelayers 11′, 21′, 12′, 22′, 13′ are pressed to one another. Duringclamping the temperature of the stack may be increased. After releasingthe pressure, a multilayer substrate exists which differs from themultilayer substrate 3 of FIG. 19 c in that the middle metal layer 12 ismade in one piece. Instead of grooves 19 the sections 12 a, 12 b, 12 cof metal layer 12 are spaced apart by spaces 16.

If, e.g., the metal layers 11′, 12′, 12″, 13′ include identicalthicknesses, the thickness d11 of the top metal layer 11 and thethickness d13 of the bottom metal layer 13 (FIGS. 19 d, 20 b) of themultilayer substrate 3 is about half the thicknesses d12 of all othermetal layers 12 of the multilayer substrate 3.

FIG. 21 illustrates different processes of a procedure for manufacturinga pre-curved multilayer substrate. The processes may be identical to theprocedures described with reference to FIGS. 19 and 20. However, thepre-curvature may be achieved by using curved clamping jaws 20 (FIG. 21a) instead of plane clamping jaws 20 described with reference to FIG. 18f. FIG. 21 b illustrates the pre-curved sub-substrate 3′ after releasingthe pressure applied by the curved clamping jaws 20. In the same way,pre-curved multilayer substrates may be produced by using curvedclamping jaws 20 instead of plane clamping jaws 20 described withreference to FIGS. 19 b and 20 b.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments shown and described withoutdeparting from the scope of the present invention. This application isintended to cover any adaptations or variations of the specificembodiments discussed herein. Therefore, it is intended that thisinvention be limited only by the claims and the equivalents thereof.

1. A semiconductor module comprising: a multilayer substrate comprising a plurality of metal layers and a plurality of ceramic layers, with a ceramic layer located between two metal layers.
 2. The module of claim 1, comprising: an integrated circuit located on the multilayer substrate.
 3. The module of claim 1, comprising: one or more semiconductor chips located on the multilayer substrate.
 4. The module of claim 1, comprising: the plurality of metal layers comprising at least a first metal layer, and second metal layer, and a third metal layer; and the plurality of ceramic layers comprising at least a first ceramic layer and a second ceramic layer.
 5. The module of claim 1, comprising: a heat sink pressed against the multilayer substrate.
 6. The module of claim 5, comprising: a paste between the heat sink and the multilayer substrate.
 7. A power semiconductor module comprising: a multilayer substrate comprising a plurality of metal layers and a plurality of ceramic layers, with each ceramic layer located between two metal layers; an electric power circuit comprising at least one power semiconductor chip; a housing cover comprising a side wall, where the side wall comprises a bottom surface facing towards the multilayer substrate; and an elastic filler which is arranged at least partly between the bottom surface of the side wall and the top surface of the second ceramic layer.
 8. The module of claim 7, comprising: the plurality of metal layers comprising at least a first metal layer, and second metal layer, and a third metal layer; and the plurality of ceramic layers comprising at least a first ceramic layer and a second ceramic layer.
 9. The power semiconductor module of claim 8, wherein the second metal layer comprises a bottom surface facing towards the second ceramic layer, the bottom surface of the second metal layer comprising an outer edge, where the elastic filler insulates at least the outer edge of the bottom surface of the second metal layer against contact with air or gas.
 10. The power semiconductor module of claim 8, comprising wherein the second metal layer is the metal layer next to the third metal layer.
 11. The power semiconductor module of claim 8, comprising wherein the second metal layer and the third metal layer are electrically connected to one another and electrically insulated against the electric power circuit.
 12. The power semiconductor module of claim 11, comprising wherein the second metal layer and the third metal layer are electrically connected to one another by at least one via formed in the second ceramic layer.
 13. The power semiconductor module of claim 7,comprising wherein the multilayer substrate forms a base plate of the power semiconductor module.
 14. The power semiconductor module of claim 7, comprising at least one power semiconductor chip, where all power semiconductor chips of the power semiconductor module are arranged on the multilayer substrate.
 15. The power semiconductor module of claim 7, comprising wherein a power semiconductor chip is defined as semiconductor chip with current ratings of more than 50 A and/or with voltage ratings of more than 500 V.
 16. The power semiconductor module of claim 7, comprising wherein a power semiconductor chip is defined as semiconductor chip with a chip size of more than 5.5 mm×5.5 mm.
 17. The power semiconductor module of claim 7, comprising wherein the multilayer substrate together with the housing cover forms a housing of the power semiconductor module.
 18. The power semiconductor module of claim 7, comprising wherein the multilayer substrate substantially extends in a plane perpendicular to the vertical direction, where the smallest dimension of the filler that appears between the bottom surface of the side wall and the multilayer substrate in the vertical direction ranges from 0.1 mm to 2 mm.
 19. The power semiconductor module of claim 8, wherein the multilayer substrate comprises a top layer which is formed by the first metal layer and which comprises conductive sections spaced apart from one another.
 20. The power semiconductor module of claim 19, comprising wherein at least one power semiconductor chip is electrically connected with one of the section of the first metal layer.
 21. The power semiconductor module of claim 19, comprising wherein the top metal layer of the multilayer substrate extends beneath a recess of the side wall of the housing cover.
 22. The power semiconductor module of claim 8, wherein at least one of the ceramic layers comprises a number of vias arranged between at least one of the power semiconductor chips and the third metal layer.
 23. The power semiconductor module of claim 22, wherein the heat conductive vias comprise diameters below 5 mm.
 24. The power semiconductor module of claim 22, wherein the heat conductive vias comprise diameters from 1 mm to 2.5 mm.
 25. The power semiconductor module of claim 7, comprising wherein the multilayer substrate is pre-curved convex relative to the center of the power semiconductor module.
 26. The power semiconductor module of claim 7, comprising wherein the multilayer substrate is pre-curved concave relative to the center of the power semiconductor module.
 27. The power semiconductor module of claim 7, wherein at least one of the metal layers consists of copper, aluminum or silver, or comprises at least one of these metals.
 28. The power semiconductor module of claim 7, wherein at least one of the ceramic layers comprises or consists of the substances Al2O3, AlN or Si3N4.
 29. The power semiconductor module of claim 7, wherein at least one of the metal layers comprises a thickness in the range from 0.05 mm to 2 mm.
 30. The power semiconductor module of claim 7, wherein where at least one of the metal layers comprises a thickness in the range from 0.25 mm to 0.5 mm.
 31. The power semiconductor module of claim 7, wherein where at least one of the ceramic layers comprises a thickness in the range from 0.1 mm to 2 mm.
 32. The power semiconductor module of claim 7, wherein where at least one of the ceramic layers comprises a thickness in the range from 0.25 mm to 1 mm.
 33. The power semiconductor module of claim 8, wherein where the third metal layer comprises a thickness of less than or equal to 2 mm.
 34. The power semiconductor module of claim 33, wherein where the third metal layer comprises a thickness of less than or equal to 1 mm.
 35. The power semiconductor module of claim 8, comprising wherein each the thickness of the first metal layer and the thickness of the third metal layer is about half the thickness of each of the additional metal layers.
 36. The power semiconductor module of claim 8, comprising wherein, except the bottom metal layer of the group of metal layers, each of the metal layers of the multilayer substrate being electrically connected to the electrical circuit is completely insulated against contact with air or gas.
 37. A power semiconductor module comprising: a multilayer substrate comprising a first group of metal layers with at least a first metal layer, a second metal layer and a third three metal layers, and a second group of ceramic layers with at least a first ceramic layer and a second two ceramic layers, where the layers of the group of metal layers and the layers of the group of ceramic layers are arranged successively in a vertical direction such that the first ceramic layer is arranged between the first metal layer and the second metal layer and that the second ceramic layer is arranged between the second metal layer and the third metal layer, all metal layers of the first group and all ceramic layers of the second group are arranged successively in a vertical direction such that between any two metal layers of the first group a ceramic layer of the second group is arranged where the third metal layer is the bottom layer of the multilayer substrate, and where the second ceramic layer comprises a top surface facing away from the third metal layer; an electric power circuit comprising at least two controllable power semiconductor chips being electrically interconnected to form a half bridge; a housing cover comprising a side wall, where the side wall comprises a bottom surface facing towards the multilayer substrate; an elastic filler which is arranged at least partly between the bottom surface of the side wall and the multilayer substrate top surface of the second ceramic layer; two power supply terminals to provide power for the half bridge; and a phase output terminal of the half bridge.
 38. The power semiconductor module of claim 37, comprising: the first metal layer is a top layer of the multilayer substrate and faces towards the housing cover; and at least one of the power supply terminals is directly welded or soldered to one of the metal layers of the multilayer substrate which is different from the first metal layer.
 39. The power semiconductor module of claim 37, comprising: the first metal layer is a top layer of the multilayer substrate and faces toward the housing cover; and at least the phase output terminal is directly soldered or welded to one of the metal layers which is different from the first metal layer.
 40. A power semiconductor module comprising: a multilayer substrate comprising a group of metal layers with at least a first metal layer, a second metal layer and a third metal layer, and a group of ceramic layers with at least a first ceramic layer and a second ceramic layer, where the layers of the group of metal layers and the layers of the group of ceramic layers are arranged successively in a vertical direction such that the first ceramic layer is arranged between the first metal layer and the second metal layer and that the second ceramic layer is arranged between the second metal layer and the third metal layer, and where the second ceramic layer comprises a top surface facing away from the third metal layer; an electric power circuit comprising at least one power semiconductor chip; a housing cover comprising a side wall, where the side wall comprises a bottom surface facing towards the multilayer substrate; and an elastic filler which is arranged at least partly between the bottom surface of the side wall and the top surface of the second ceramic layer; where the third metal layer comprises a thickness of less than or equal to 2 mm and forms an outer surface layer of the power semiconductor module.
 41. The power semiconductor module of claim 40, comprising wherein the multilayer substrate is formed convex relative to the center of the power semiconductor module.
 42. The power semiconductor module of claim 40, comprising wherein the multilayer substrate is formed concave relative to the center of the power semiconductor module.
 43. A power semiconductor arrangement comprising: a multilayer substrate comprising a group of metal layers with at least a first metal layer, a second metal layer and a third metal layer, and a group of ceramic layers with at least a first ceramic layer and a second ceramic layer, where the layers of the group of metal layers and the layers of the group of ceramic layers are arranged successively in a vertical direction such that the first ceramic layer is arranged between the first metal layer and the second metal layer and that the second ceramic layer is arranged between the second metal layer and the third metal layer, where the third metal layer is the bottom layer of the multilayer substrate, and where the second ceramic layer comprises a top surface facing away from the third metal layer; an electric power circuit comprising at least one power semiconductor chip; a housing cover comprising a side wall, where the side wall comprises a bottom surface facing towards the multilayer substrate; an elastic filler which is arranged at least partly between the bottom surface of the side wall and the top surface of the second ceramic layer; and a heat sink against which the power semiconductor module is pressed with the multilayer substrate ahead.
 44. The power semiconductor arrangement of claim 43, wherein the second metal layer comprises a bottom surface facing towards the second ceramic layer, the bottom surface of the second metal layer comprising an outer edge, where the elastic filler insulates at least the outer edge of the bottom surface of the second metal layer against contact with air or gas.
 45. The power semiconductor arrangement of claim 43, comprising wherein the second metal layer is the metal layer next to the third metal layer.
 46. The power semiconductor arrangement of claim 43, comprising wherein the second metal layer and the third metal layer are electrically connected to one another and electrically insulated against the electric power circuit.
 47. The power semiconductor arrangement of claim 43, comprising wherein the second metal layer and the third metal layer are electrically connected to one another by at least one via formed in the second ceramic layer.
 48. The power semiconductor arrangement of claim 43, comprising wherein the multilayer substrate forms a base plate of the power semiconductor module.
 49. The power semiconductor arrangement of claim 43, comprising wherein a layer of heat conductive paste is arranged between the multilayer substrate and the heat sink.
 50. The power semiconductor arrangement of claim 43, comprising wherein the power semiconductor module is detachable connected with the heat sink.
 51. The power semiconductor arrangement of claim 43, comprising wherein, except the bottom metal layer of the group of metal layers, each of the metal layers of the multilayer substrate being electrically connected to the electrical circuit is completely insulated against contact with air or gas.
 52. The power semiconductor arrangement of claim 43, wherein the metal layer next to the heat sink comprises a thickness of less than or equal to 2 mm.
 53. A multilayer substrate to be used as base plate for a power semiconductor module comprising: a group of metal layers with at least a first metal layer; a second metal layer and a third metal layer a group of ceramic layers with at least a first ceramic layer and a second ceramic layer, where the layers of the group of metal layers and the layers of the group of ceramic layers are arranged successively in a vertical direction such that the first ceramic layer is arranged between the first metal layer and the second metal layer and that the second ceramic layer is arranged between the second metal layer and the third metal layer, where the third metal layer comprises a thickness of less than or equal to 2 mm and forms an outer surface layer of multilayer substrate, and where the second metal layer and the third metal layer are electrically connected.
 54. The multilayer substrate of claim 53, comprising wherein the second metal layer and the third metal layer are electrically connected by at least one via.
 55. The multilayer substrate of claim 53, comprising wherein the second metal layer and the third metal layer are electrically insulated against the first metal layer.
 56. The multilayer substrate of claim 53, comprising being formed convex relative to the third metal layer.
 57. The multilayer substrate of claim 53, comprising being formed concave relative to the third metal layer.
 58. A method for producing a power semiconductor module comprising: providing a multilayer substrate comprising a group of metal layers with at least a first metal layer, a second metal layer and a third metal layer, and a group of ceramic layers with at least a first ceramic layer and a second ceramic layer, where the layers of the group of metal layers and the layers of the group of ceramic layers are arranged successively in a vertical direction such that the first ceramic layer is arranged between the first metal layer and the second metal layer and that the second ceramic layer is arranged between the second metal layer and the third metal layer; providing at least one power semiconductor chip; providing a housing cover comprising an upper side and a side wall, where the side wall comprises a bottom surface facing away from the upper side; providing an elastic filler; forming an electric power circuit comprising the at least one power semiconductor chip; and assembling the populated multilayer substrate and the housing cover by arranging the elastic filler at least partly between the bottom surface of the side wall and the top surface of the second ceramic layer, where the multilayer substrate is arranged such that the third metal layer faces away from the upper side of the housing cover.
 59. A method for producing a multilayer substrate to be used as base plate for a power semiconductor module comprising: providing at least a first metal layer, a second metal layer and a third metal layer, the first metal layer and the third metal layer each comprising a thickness of less than or equal to 2 mm; providing at least a first ceramic layer and a second ceramic layer; forming a stack by arranging the first ceramic layer between the first metal layer and the second metal layer and the second ceramic layer between the second metal layer and the third metal layer; and joining the first metal layer, the second metal layer, the third metal layer, the first ceramic layer and the second ceramic layer to one another.
 60. The method of claim 59, comprising electrically connecting the second metal layer and the third metal layer to one another.
 61. The method of claim 60, comprising electrically connecting the second metal layer and the third metal layer to one another by at least one via.
 62. The method of claim 59, comprising forming the stack by stacking at least two sub-substrates, where each of the sub-substrates comprises: at least one of the first ceramic layer and the second ceramic layer; and at least one of the first metal layer, the second metal layer and the third metal layer.
 63. The method of claim 59, comprising forming the stack by stacking at least two sub-substrates, where at least one of the sub-substrates comprises: exactly one of the first ceramic layer and the second ceramic layer; and exactly one of the first metal layer, the second metal layer and the third metal layer.
 64. The method of claim 59, comprising forming the stack by stacking at least two sub-substrates, where at least one of the sub-substrates comprises: exactly two of the first metal layer, the second metal layer and the third metal layer; and exactly one of the first ceramic layer and the second ceramic layer, where the exactly one of the ceramic layers is arranged between the exactly two of the metal layers.
 64. The method of claim 59, comprising joining the first metal layer, the second metal layer, the third metal layer, the first ceramic layer and the second ceramic layer by active metal brazing (AMB) or by direct aluminum bonding (DAB) or by direct copper bonding (DCB) or by low temperature joining (LTJT) or by transient liquid phase soldering (TLP) or by vacuum soldering or by gluing.
 65. The method of claim 59, comprising clamping the stack during joining the first metal layer, the second metal layer, the third metal layer, the first ceramic layer and the second ceramic layer under pressure between two clamping jaws.
 66. The method of claim 65, comprising curving the clamping jaws on the sides facing towards the stack. 